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91609hkim 20090831-s00003 no.a1335-1/21 ver.1.01 lc87f2708a overview the lc87f2708a is an 8-bit microcotroller that, centered around a cpu running at a minimum bus cycle time of 100ns, integrates on a single chip a number of hardware features such as 8k-byte flash rom (onboard programmable), 512-byte ram, an on-chip debugger, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be divide d into 8-bit timers or pwms), a synchronou s sio interface, a high- speed 12-bit pwm, two high-speed pulse width/period counters, a 7-channel ad converter with 12-/8-bit resolution selector, an analog comparator, a watchdog timer, an intern al reset circuit, a system clock frequency divider, and a 16-source 10-vector interrupt feature. features ? flash rom ? capable of on-board programming of voltage source (3.0 to 5.5v) ? block-erasable in 128 byte units ? 8192 8 bits ? ram ? 512 9 bits ordering number : ena1335a cmos ic from 8k byte, ram 512 byte on-chip 8-bit 1-chip microcontroller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
lc87f2708a no.a1335-2/21 ? minimum bus cycle time note1 ? 100ns (10mhz) v dd =2.7 to 5.5v note2 ? minimum instruction cycle time ? 300ns (10mhz) v dd =2.7 to 5.5v note2 note1: the bus cycle time here refers to the rom read speed. note2: use this product in a voltage range of 3.0 to 5.5v because the mini mum release voltage (porrl) of the power-on reset (por) circuit is 2.87v 0.12v. ? ports ? i/o ports ports whose i/o direction can be designated in 1-bit units 11 (p10 to p16, p30 to p33) ? reset pins 1 ( res ) ? power pins 2 (v ss 1, v dd 1) ? timers ? timer 0: 16-bit timer/counter with a capture register. mode 0: 8-bit timer with an 8-bit programmab le prescaler (with an 8-bit capture register) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programma ble prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ? timer 1: 16-bit timer/counter that can provide with pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescal er (with toggle out puts) + 8-bit timer/ counter with an 8-bit pres caler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle output also possible from the lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (lower-order 8 bits may be used as pwm) ? serial interface ? sio7: 8-bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3 tcyc) ? high-speed 12-bit pwm ? system clock/high-speed rc oscillation clock (20mhz or 40mhz) operation selectable ? duty/period programmable ? continuous pwm output/specific count pwm output (automatic stop) selectable ? high-speed pulse/period counter ? hct1: high-speed pulse width/period counter 1 1) system clock/high-speed rc oscillation clock (20mhz or 40mhz) operation selectable 2) h-level width/l-level width/period measurement modes selectable 3) input triggering noise filter ? hct2: high-speed pulse width/period counter 2 1) system clock/high-speed rc oscillation clock (20mhz or 40mhz) operation selectable 2) can measure both l-level width and period simultaneously. 3) input triggering noise filter 4) input trigger selectable (from 3 signals, i.e., p11/hct2in, p31/hct2in, and analog comparator output) ? ad converter: 12 bits 7 channels ? 12-/8-bits ad converter resolution selectable ? analog comparator ? sends output to the p32/cmpo port (polarity selectable). ? edge detection function (shared with intc and also allows the selection of the noise filter function)
lc87f2708a no.a1335-3/21 ? watchdog timer ? can generate the internal reset signal on a timer ove rflow monitored by the wdt-dedicated low-speed rc oscillation clock (30khz). ? allows selection of continue, stop, or hold mode operation of the counter on entry into the halt/ hold mode. ? interrupts source flags ? 16 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l inta 2 0000bh x or l intb 3 00013h h or l intc/t0l/inte 4 0001bh h or l intd/intf 5 00023h h or l t0h/sio7 6 0002bh h or l t1l/t1h 7 00033h h or l hct1 8 0003bh h or l hct2 9 00043h h or l adc/hpwm automatic stop/hpwm cycle 10 0004bh h or l none ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 256levels maximum (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? medium speed rc oscillation circuit (internal): for system clock (1mhz) ? low speed rc oscillation circuit (int ernal): for watchdog timer (30khz) ? high speed rc oscillation circuit (internal): for system clock (20mhz or 40mhz) 1) 2 source oscillation frequencies (20mhz or 40mhz) sel ectable for the high-speed rc oscillation circuit by optional configuration. ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (when high speed rc oscillation is selected for system clock.). ? internal reset circuit ? power-on reset (por) function 1) por reset is generated only at power-on time. 2) the por release level can be selected from 3 levels (2.87v, 3.86v, and 4.35v) by optional configuration. ? low-voltage detection reset (lvd) function 1) lvd and por functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) the use or disuse of the lvd function and the low voltage threshold level (3 levels: 2.81v, 3.79v and 4.28v). can be selected by optional configuration.
lc87f2708a no.a1335-4/21 ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are the following three ways of resetting the halt mode. (1) setting the reset pin to the low level (2) generating a reset signal via the watchdog timer or brown-out detector (3) having an interrupt generated ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the medium- and high-speed rc oscillation circuits automatically stop operation. 2) there are the following four ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) generating a reset signal via the watchdog timer or brown-out detector (3) setting at least one of the inta, intb, intc, in td, inte, and intf pins to the specified level (inta and intb hold mode reset is available only when level detection is set.) (4) applying input signals to the in+ and in- pins so that the analog comparator output is set to the specified level (when the analog comparator outp ut is assigned to the intc input) ? on-chip debugger function ? supports software debugging with the ic mounted on the target board (lc87d2708a). lc87f2708a has an on-chip debugger but its function is limited. ? 3 channels of on-chip debugger pins are available. ? data security function note3 ? protects the program data stored in flash memory from unauthorized read or copy. note3: this data security function does not necessarily provide absolute data security. ? package form ? mfp14s(225mil): lead-free type ? development tools on-chip debugger: 1) tcb87-type b + lc87d2708a 2) tcb87-type b + lc87f2708a 3) tcb87-type c (3 wire version) + lc87d2708a 4) tcb87-type c (3 wire version) + lc87f2708a ? programming board package programming board mfp14s(225mil) w87f27m-dbg ? flash rom programming board maker model version device af9101/af9103 (main body) (fsg models) flash support group, inc. (fsg) + sanyo (note 4) in-circuit programmer sib87 (inter face driver) (sanyo model) (note 5) lc87f2708a single/gang programmer sanyo in-circuit/ gang programmer skk-dbg type b (sanyo fws) application version 1.04 or later chip data version 2.10 or later lc87f2708a for information about af-series: flash support group, inc. tel: +81-53-459-1050 e-mail: sales@j-fsg.co.jp note4: on-board-programmer from fsg (af9101/af91 03) and serial interface driv er from sanyo (sib87) together can give a pc-less, standalone on-board-programming capabilities. note5: it needs a special programming devices and applications depending on the use of programming environment. please ask fsg or sanyo for the information.
lc87f2708a no.a1335-5/21 package dimensions unit : mm (typ) 3111a pin assignment sanyo: mfp14s(225mil) ?lead-free type? mfp14s name mfp14s name 1 p31/intb/hct2in/dbgp01 8 p14/inte/t1pwmh/an4/dbgp21 2 p30/inta/hct1in/dbgpx0 9 p13/intf/t1pwml/an3/dbgp20 3 res 10 p12/sck7/intf/in0-/an2 4 p10/so7/inte/an0/dbgp02 11 p11/si7/sb7/inte/i n0+/hct2in/an1 5 v ss 1 12 p33/intd/hpwm/dbgp12 6 p16/intf/in1-/an6 13 p32/intc/cmpo/dbgp11 7 p15/inte/in1+/an5/dbgp22 14 v dd 1 p31/intb/hct2in/dbgp01 p30/inta/hct1in/dbgpx0 res p10/so7/inte/an0/dbgp02 v ss 1 p16/intf/in1-/an6 p15/inte/in1+/an5/dbgp22 v dd 1 p32/intc/cmpo/dbgp11 p33/intd/hpwm/dbgp12 p11/si7/sb7/inte/in0+/hct2in/an1 p12/sck7/intf/in0-/an2 p13/intf/t1pwml/an3/dbgp20 p14/inte/t1pwmh/an4/dbgp21 1 2 3 4 5 6 7 14 13 12 11 10 9 8 top view lc87f2708a sanyo : mfp14s(225mil) 1 14 7 8 8.0 0.15 (1.0) 1.0 0.35 1.7max (1.5) 0.1 4.4 0.63 6.4
lc87f2708a no.a1335-6/21 system block diagram interrupt control standby control ir pla flash rom pc bus interface port 1 (inte to intf) port 3 (inta to intd) sio7 timer 0 timer 1 high-speed pwm high-speed pulse width/period counter1 adc high-speed pulse width/period counter2 acc b register c register psw rar ram stack pointer alu on-chip debugger medium- speed rc freq. divider clock generator reset circuit (lvd/por) wdt (low-speed rc) reset control res data bus data bus analog comparator high-speed rc
lc87f2708a no.a1335-7/21 pin description pin name i/o description option v ss 1 - - power supply pin no v dd 1 - + power supply pin no port1 p10 to p16 i/o ? 7-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? multiplexed pins p10: sio7 data output p11: sio7 data input/bus i/o/high-speed pulse width/period counter 2 input p12: sio7 clock i/o p13: timer 1 pwml output p14: timer 1 pwmh output p10, p11, p14, p15: inte input/hold release input/timer 1 event input/timer 0l capture input/ timer 0h capture input p12, p13, p16: intf input/hold release input/timer 1 ev ent input/timer 0l capture input/ timer 0h capture input ad converter input port: an0 to an6(p10 to p16) analog comparator input port 0: in0+, in0-(p11, p12) analog comparator input port 1: in1+, in1-(p15, p16) on-chip debugger pin 1: dbgp02 (p10) on-chip debugger pin 3: dbgp20 to dbgp22 (p13 to p15) ? interrupt acknowledge type rising falling rising & falling h level l level inte enable enable enable disable disable intf enable enable enable disable disable yes port3 p30 to p33 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? multiplexed pins p30: inta input/hold release input/timer 0l capture input/high-speed pulse width/ period counter 1 input p31: intb input/hold release input/timer 0h capture input/high-speed pulse width/ period counter 2 input p32: intc input/hold release input/time r 0 event input/timer 0l capture input/ analog comparator output p33: intd input/hold release input/timer 0 event input/timer 0h capture input/ high-speed pwm output on-chip debugger pin 1: dbgpx0 to dbgp01 (p30 to p31) on-chip debugger pin 2: dbgpx0 to dbgp12 (p30, p32 to p33) ? interrupt acknowledge type rising falling rising & falling h level l level inta enable enable disable enable enable intb enable enable disable enable enable intc enable enable enable disable disable intd enable enable enable disable disable yes res i/o external reset input/internal reset output no
lc87f2708a no.a1335-8/21 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option sselected in units of option type output type pull-up resistor 1 cmos programmable p10 to p16 1 bit 2 nch-open drain programmable 1 cmos programmable p30 to p33 1 bit 2 nch-open drain programmable on-chip debugger pin processing for the processing of the on-chip debugger pins, refer to the separately available documents entitled "rd87 on-chip debugger installation" and "lc872000 series on-chip debugger pin processing." recommended unused pin connections recommended unused pin connections pin name board software p10 to p16 open set output low p30 to p33 open set output low user option table option name option type flash version option switched in unit of description cmos p10 to p16 { 1 bit nch-open drain cmos port output type p30 to p33 { 1 bit nch-open drain 00000h program start address - { - 01e00h enable: used brown-out detector function { - disable: not used brown-out detector reset function brown-out trip level { - 3 levels power-on-reset function power-on-reset level { - 3 levels 20 mhz high-speed rc oscillator circuit oscillation frequency { - 40 mhz
lc87f2708a no.a1335-9/21 absolute maximum ratings at ta = 25 c, v ss 1 =0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1 -0.3 +6.5 input voltage v i res -0.3 v dd +0.3 input/output voltage v io ? port 1 ? port 3 -0.3 v dd +0.3 v ioph(1) port 1 cmos output selected per applicable pin -7.5 peak output current ioph(2) port 3 cmos output selected per applicable pin -10 iomh(1) port 1 cmos output selected per applicable pin -5 mean output current (note 1-1) iomh(2) port 3 cmos output selected per applicable pin -7.5 ioah(1) ? ports 10, 15, 16 ? ports 30, 31 total of currents at all applicable pins -20 ioah(2) ? ports 11 to 14 ? ports 32, 33 total of currents at all applicable pins -20 high level output current total output current ioah(3) ? port 1 ? port 3 total of currents at all applicable pins -35 iopl(1) port 1 per applicable pin 15 peak output current iopl(2) port 3 per applicable pin 10 ioml(1) port 1 per applicable pin 10 mean output current (note 1-1) ioml(2) port 3 per applicable pin 7.5 ioal(1) ? port 10 ? ports 30, 31 total of currents at all applicable pins 25 ioal(2) ? ports 11 to 16 ? ports 32, 33 total of currents at all applicable pins 35 low level output current total output current ioal(3) ? port 1 ? port 3 total of currents at all applicable pins 55 ma pd max(1) ? ta=-40 to +85 c ? independent package 113 power dissipation pd max(2) mfp14s(225mil) ? ta=-40 to +85 c ? mounted on thermal test board ? (note 1-2) 260 mw operating ambient temperature topr -40 +85 storage ambient temperature tstg -55 +125 c note 1-1: the mean output current is a mean value measured over 100ms . note 1-2: thermal test board used conforms to semi (size: 76.1 114.3 1.6tmm, glass epoxy board).
lc87f2708a no.a1335-10/21 allowable operating range at ta = -40 to +85 c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit operating supply voltage (note 2-1) v dd v dd 1 0.272 s tcyc 100 s 2.7 5.5 memory sustaining supply voltage v hd v dd 1 ram and register contents sustained in hold mode 2.0 5.5 v ih (1) ? port 1 ? port 3 output disabled 2.7 to 5.5 0.3v dd +0.7 v dd high level input voltage v ih (2) res 2.7 to 5.5 0.75v dd v dd 4.0 to 5.5 v ss 0.1v dd +0.4 v il (1) ? port 1 ? port 3 output disabled 2.7 to 4.0 v ss 0.2v dd low level input voltage v il (2) res 2.7 to 5.5 v ss 0.25v dd v instruction cycle time (note 2-2) tcyc 2.7 to 5.5 0.272 100 s fmhrc(1) ? high-speed rc oscillation ? 40mhz selected as option ? ta=-20 to +85 c 4.5 to 5.5 38 40 42 fmhrc(2) 4.5 to 5.5 37.6 40 42.4 fmhrc(3) 3.5 to 5.5 36.8 40 43.2 fmhrc(4) ? high-speed rc oscillation ? 40mhz selected as option ? ta=-40 to +85 c 2.7 to 5.5 32 40 43.2 fmhrc(5) ? high-speed rc oscillation ? 20mhz selected as option ? ta=-20 to +85 c 3.0 to 5.5 19 20 21 fmhrc(6) ? high-speed rc oscillation ? 20mhz selected as option ? ta=-40 to +85 c 2.7 to 5.5 18.7 20 21.3 fmrc medium-speed rc oscillation 2.7 to 5.5 0.5 1.0 2.0 mhz oscillation frequency range fmslrc low-speed rc oscillation 2.7 to 5.5 15 30 60 khz oscillation stabilization time tmshrc ? when high-speed rc oscillation state is switched from stopped to enabled. ? see fig. 2. 2.7 to 5.5 100 s note 2-1: use this product in a voltage range of 3.0 to 5.5v because the minimum release voltage (porrl) of the power-on reset (por) circuit is 2.87v 0.12v. note 2-2: relationship between tcyc and oscillation frequency is as follows: ? when system clock source is set to medium-speed rc oscillation 3/fmrc at a division ratio of 1/1, 6/fmrc at a division ratio of 1/2, 12/fmrc a division ratio of 1/4, and so forth ? when system clock source is set to high-speed rc osc illation (40mhz selected by optional configuration) 12/fmhrc at a division ratio of 1/1, 24/fmhrc at a division ratio of 1/2, 48/fmhrc a division ratio of 1/4, and so forth ? when system clock source is set to high-speed rc osc illation (20mhz selected by optional configuration) 6/fmhrc at a division ratio of 1/1, 12/fmhrc at a division ratio of 1/2, 24/fmhrc a division ratio of 1/4, and so forth
lc87f2708a no.a1335-11/21 electrical characteristics at ta = -40 to +85 c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ? port 1 ? port 3 ? output disabled ? pull-up resistor off ? v in =v dd (including output tr. off leakage current) 2.7 to 5.5 1 high level input current i ih (2) res v in =v dd 2.7 to 5.5 1 low level input current i il ? port 1 ? port 3 ? output disabled ? pull-up resistor off ? v in =v ss (including output tr. off leakage current) 2.7 to 5.5 -1 a v oh (1) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (2) cmos output type port 1 i oh =-0.35ma 2.7 to 5.5 v dd -0.4 v oh (3) i oh =-5ma 4.5 to 5.5 v dd -1.5 high level output voltage v oh (4) cmos output type port 3 i oh =-0.7ma 2.7 to 5.5 v dd -0.4 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) port 1 i ol =1.4ma 2.7 to 5.5 0.4 v ol (3) i ol =5ma 4.5 to 5.5 1.5 low level output voltage v ol (4) port 3 i ol =0.7ma 2.7 to 5.5 0.4 v rpu(1) 4.5 to 5.5 15 35 80 rpu(2) ? port 1 ? port 3 2.7 to 4.5 18 50 150 pull-up resistance rpu(3) res v oh =0.9v dd 2.7 to 5.5 216 360 504 k hysteresis voltage vhys ? port 1 ? port 3 ? res 2.7 to 5.5 0.1v dd v pin capacitance cp all pins ? v in =v ss for pins other than that under test ? f=1mhz ? ta=25 c 2.7 to 5.5 10 pf
lc87f2708a no.a1335-12/21 serial i/o characteristics at ta = -40 to +85 c, v ss 1 = 0v 1. sio7 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 input clock high level pulse width tsckh(1) sck7(p12) ? see fig. 4 (note 4-1-2) 2.7 to 5.5 1 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 serial clock output clock high level pulse width tsckh(2) sck7(p12) ? cmos output selected ? see fig. 4. 2.7 to 5.5 1/2 tsck data setup time tsdi(1) 0.03 serial input data hold time thdi(1) sb7(p11), si7(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 4. 2.7 to 5.5 0.03 input clock tddo(1) 1tcyc +0.05 serial output output clock output delay time tddo(2) so7(p10), sb7(p11) ? must be specified with respect to rising edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode ? see fig. 4. 2.7 to 5.5 (1/3)tcyc +0.05 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in transmission/reception mode, the tim e from si7run being set when serial clock is "h" to the first falling edge of the serial clock must be longer than 1tcyc.
lc87f2708a no.a1335-13/21 pulse input conditions at ta = -40 to +85 c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min. typ. max. unit tpih(1) tpil(1) inta(p30), intb(p31), intd(p33), inte (p10, p11, p14, p15), intf(p12, p13, p16) ? interrupt source flag can be set. ? event inputs for timers 0 and 1 are enabled. 2.7 to 5.5 1 tpih(2) tpil(2) intc(p32) when noise filter time constant is "none" ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 1 tpih(3) tpil(3) intc(p32) when noise filter time constant is "1/16" ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 64 tpih(4) tpil(4) intc(p32) when noise filter time constant is "1/32" ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 128 tpih(5) tpil(5) intc(p32) when noise filter time constant is "1/64" ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 256 tcyc tpih(6) tpil(6) hct1in(p30) pulses can be recognized as signals by the high-speed pulse width/period counter 1. 2.7 to 5.5 3 h1ck (note 5-1) tpih(7) tpil(7) hct2in(p11, p31) pulses can be recognized as signals by the high-speed pulse width/period counter 2. 2.7 to 5.5 6 h2ck (note 5-2) high/low level pulse width tpil(8) res resetting is enabled. 2.7 to 5.5 200 s note 5-1: h1ck denotes the period of the base clock (1 to 8 high-speed rc oscillation clock or system clock) for the high-speed pulse width/period counter 1. note 5-2: h2ck denotes the period of the base clock (2 to 16 high-speed rc oscillation clock or system clock) for the high-speed pulse width/period counter 2. comparator characteristics at ta = -40 to +85 c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit common mode input voltage range vcmin 2.7 to 5.5 v ss v dd -1.5 v offset voltage voff in0+(p11), in0-(p12), in1+(p15), in1-(p16) within common mode input voltage range 2.7 to 5.5 10 30 mv response time trt ? within common mode input voltage range ? input amplitude=100mv ? overdrive=50mv 2.7 to 5.5 200 600 ns operation stabilization time (note 6-1) tcmw 2.7 to 5.5 1.0 s note 6-1: the interval after cmpon is set till the operation gets stabilized.
lc87f2708a no.a1335-14/21 ad converter characteristics at v ss 1 = 0v <12-bits ad converter mode/ta = -40 to +85 c > specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 12 bit absolute accuracy et (note 7-1) 3.0 to 5.5 16 lsb 4.0 to 5.5 38 104.3 conversion time tcad ? see conversion time calculation method ? (note 7-2) 3.0 to 5.5 75.8 104.3 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p10) to an6(p16) vain=v ss 3.0 to 5.5 -1 a <8-bits ad converter mode/ta = -40 to +85 c > specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute accuracy et (note 7-1) 3.0 to 5.5 1.5 lsb 4.0 to 5.5 23.4 64.3 conversion time tcad ? see conversion time calculation method . ? (note 7-2) 3.0 to 5.5 46.7 64.3 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p10) to an6(p16) vain=v ss 3.0 to 5.5 -1 a conversion time calculation formulas: 12-bits ad converter mode: tcad(conversion time) = ((52/(division ratio)) + 2) (1/3) tcyc 8-bits ad converter mode: tcad(conve rsion time) = ((32/(division ratio))+2) (1/3) tcyc conversion time (tcad) high-speed rc oscillation (fmhrc) supply voltage range (v dd ) system clock division ratio (sysdiv) cycle time (tcyc) ad division ratio (addiv) 12-bits ad 8-bits ad 4.0v to 5.5v 1/1 300ns 1/8 41.8 s 25.8 s 40mhz/20mhz 3.0v to 5.5v 1/1 300ns 1/16 83.4 s 51.4 s note 7-1: the quantization error (1/ 2lsb) is excluded from the absolute accuracy. the absolute accuracy is measured when no change occurs in the i/o state of the pins that are ad jacent to the analog input channel during ad conversion processing. note 7-2: the conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital conversion value against the analog input value is loaded in the result register. * the conversion time is 2 times the normal-time conversion time when: ? the first ad conversion is performed in the 12 -bit ad conversion mode after a system reset. ? the first ad conversion is performed after the ad conversion mode is switched from 8-bit to 12-bit conversion mode.
lc87f2708a no.a1335-15/21 power-on reset (por) characteristics at ta = -40 to +85 c, v ss 1 = 0v specification parameter symbol pin/remarks conditions option selected voltage min typ max unit 2.87v 2.75 2.87 2.99 3.86v 3.73 3.86 3.99 por release voltage porrl ? option selected ? see fig. 6. (note 8-1) 4.35v 4.21 4.35 4.49 detection voltage unknown state pouks ? see fig. 6 (note 8-2) 0.7 0.95 v power supply rise time poris power startup time from v dd =0v to 2.8v. 100 ms note 8-1: the por release voltage can be selected from three levels when the low-voltage detection feature is deselected. note 8-2: there is an unpredictable period before the power-on reset transistor starts to turn on. low voltage detection reset (lvd) characteristics at ta = -40 to +85 c, v ss 1 = 0v specification parameter symbol pin/remarks conditions option selected voltage min typ max unit 2.81v 2.71 2.81 2.91 3.79v 3.69 3.79 3.89 lvd reset voltage (note 9-2) lvdet 4.28v 4.18 4.28 4.38 v 2.81v 60 3.79v 65 lvd voltage hysteresis lvhys ? option selected. ? see fig. 7. (note 9-1) (note 9-3) 4.28v 65 mv detection voltage unknown state lvuks ? see fig. 7. (note 9-4) 0.7 0.95 v minimum low voltage detection width (response sensitivity) tlvdw ? lvdet-0.5v ? see fig. 8. 0.2 ms note 9-1: the lvd reset voltage can be selected from three levels when the low-voltage detection feature is selected. note 9-2: the hysteresis voltage is not included in the lvd reset voltage value. note 9-3: there are cases when the lvd reset voltage value is exceeded when a gr eater change in the output level or large current is applied to the port. note 9-4: there is an unpredictable period before the low-voltage detection resetting transistor starts to run.
lc87f2708a no.a1335-16/21 consumption current characteristics at ta = -40 to +85 c, v ss 1 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddop(1) 4.5 to 5.5 7.8 14 iddop(2) ? fmhrc=40mhz oscillation mode ? system clock set to high-speed rc, 10mhz (1/4 of 40mhz) ? medium-speed rc oscillation stopped ? system clock frequency division ratio set to 1/1 2.7 to 3.6 4.9 9.4 iddop(3) 4.5 to 5.5 7.1 12.8 iddop(4) ? fmhrc=20mhz oscillation mode ? system clock set to high-speed rc, 10mhz (1/2 of 20mhz) ? medium-speed rc oscillation stopped ? system clock frequency division ratio set to 1/1 2.7 to 3.6 4.5 8.6 iddop(5) 4.5 to 5.5 0.60 1.9 normal mode consumption current (note 10-1) iddop(6) ? high-speed rc oscillation stopped ? system clock set to medium-speed rc oscillation mode ? system clock frequency division ratio set to 1/2 2.7 to 3.6 0.38 1.3 iddhalt(1) 4.5 to 5.5 3.2 5.0 iddhalt(2) halt mode ? fmhrc=40mhz oscillation mode ? system clock set to high-speed rc, 10mhz (1/4 of 40mhz) ? medium-speed rc oscillation stopped ? system clock frequency division ratio set to 1/1 2.7 to 3.6 2.0 3.1 iddhalt(3) 4.5 to 5.5 2.5 3.9 iddhalt(4) halt mode ? fmhrc=20mhz oscillation mode ? system clock set to high-speed rc, 10mhz (1/2 of 20mhz) ? medium-speed rc oscillation stopped ? system clock frequency division ratio set to 1/1 2.7 to 3.6 1.6 2.5 iddhalt(5) 4.5 to 5.5 0.32 1.0 halt mode consumption current (note 10-1) iddhalt(6) halt mode ? high-speed rc oscillation stopped ? system clock set to medium-speed rc oscillation mode ? system clock frequency division ratio set to 1/2 2.7 to 3.6 0.16 0.55 ma iddhold(1) 4.5 to 5.5 0.04 3.0 iddhold(2) hold mode ? ta=-10 to +50 c 2.7 to 3.6 0.02 1.8 iddhold(3) 4.5 to 5.5 0.04 34 iddhold(4) hold mode ? ta=-40 to +85 c 2.7 to 3.6 0.02 22 iddhold(5) 4.5 to 5.5 3.1 6.8 iddhold(6) hold mode ? lvd option selected ? ta=-10 to +50 c 2.7 to 3.6 2.4 4.2 iddhold(7) 4.5 to 5.5 3.1 39 iddhold(8) hold mode ? lvd option selected ? ta=-40 to +85 c 2.7 to 3.6 2.4 25 iddhold(9) 4.5 to 5.5 3.4 10 iddhold(10) hold mode ? watchdog timer active ? ta=-10 to +50 c 2.7 to 3.6 1.7 6.0 iddhold(11) 4.5 to 5.5 3.4 42 iddhold(12) hold mode ? watchdog timer active ? ta=-40 to +85 c 2.7 to 3.6 1.7 27 iddhold(13) 4.5 to 5.5 110 160 hold mode consumption current (note 10-1) iddhold(14) v dd 1 hold mode ? comparator active (in+=v dd , in-=v ss ) 2.7 to 3.6 65 100 a note 10-1: the consumption current value includes none of the currents that flow into the output tr and internal pull-up resistors.
lc87f2708a no.a1335-17/21 f-rom programming characteristics at ta = +10 to +55 c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit onboard programming current iddfw v dd 1 ? microcontroller consumption current is excluded. 3.0 to 5.5 5 10 ma tfw(1) ? erase operation 20 30 ms programming time tfw(2) ? programming operation 3.0 to 5.5 40 60 s power pin treatment recommendations (v dd 1, v ss 1) connect bypass capacitors that meet the following conditions between the v dd 1 and v ss 1 pins: ? connect among the v dd 1 and v ss 1 pins and bypass capacitors c1 and c2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as equal as possible (l1=l1', l2=l2'). ? connect a large-capacity cap acitor c1 and a small-capacity capacitor c2 in parallel. the capacitance of c2 should be approximately 0.1 f. v ss 1 v dd 1 l1? l2? l1 l2 c1 c2
lc87f2708a no.a1335-18/21 figure 1 ac timing measurement point reset time and oscillation stabilization time hold release signal and oscillation stabilization time figure 2 oscillation stabilization times 0.5v dd power res medium-speed rc oscillation high-speed rc oscillation operating mode reset time tmshrc unpredictable reset instruction execution v dd operating v dd lower 0v medium-speed rc oscillation high-speed rc oscillation state hold/halt release signal no hold release signal hold release signal valid hold halt instruction execution tmshrc halt release signal valid
lc87f2708a no.a1335-19/21 figure 3 sample reset circuit figure 4 serial i/o waveforms figure 5 pulse input timing signal waveform c res v dd r res res note: the external peripheral circuit differs depending on the way in which the power-on reset and low-voltage detection reset functions are used. refer to the chapter, entitled "reset function", of the user's manual. di0 di7 di2 di3 di4 di5 di6 do0 do7 do2 do3 d o4 do5 do6 di1 do1 sioclk: datain: dataout: dataout : datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tpil tpih
lc87f2708a no.a1335-20/21 figure 6 example of por only (lvd deselected) mode waveforms (at reset pin with r res pull-up resistor only) ? the por circuit generates a reset signal only when the power voltage is raised from the v ss level. ? no stable reset signal is generated if power is turned on again when the power voltage does not go down to the v ss level as shown in (a). if this case is anticipated, use th e lvd function as explained belo w or configure an external reset circuit. ? a reset is effected only when power is turned on agai n after the power voltage goes down to and remains at the v ss level for 100 s or longer as shown in (b). figure 7 example of por + lvd mode waveforms (at reset pin with r res s pull-up resistor only) ? a reset is effected both when power is turned on and when it goes down. ? the hysteresis width (lvhys) is introduced in the lvd circu it to prevent the iterations of the ic entering and exiting the reset state near the detection threshold level. por release voltage ( p o rrl ) v dd res reset unknown-state ( pouks ) (a) (b) reset period reset period 100 s or longer v dd res lvd hysteresis width (lvhys) reset unknown-state ( lvuks ) reset period reset period reset period lvd release voltage (lvdet+lvhys) lvd voltage (lvdet)
lc87f2708a no.a1335-21/21 figure 8 minimum low voltage detection width (example of short interruption of power/power fluctuation waveform) ps this catalog provides information as of august, 2009. specifications and information herein are subject to change without notice. v dd lvd voltage tlvdw v ss lvd release voltage lvdet-0.5v sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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